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X25F047
SPI SerialFlash with Block LockTM Protection
DESCRIPTION
512 x 8 Bit
FEATURES * 1MHz Clock Rate * SPI Modes (0,0 & 1,1) * 512 x 8 Bits --16 Byte Small Sector Program Mode * Low Power CMOS --<1A Standby Current --<3mA Active Current during Program --<400A Active Current during Read * 1.8V to 3.6V or 5V "Univolt" Read and Program Power Supply Versions * Block Lock Protection --Block Lock Protect 0, any 1/4, 1st 1/2, First or Last Sector of SerialFlash Array * Built-in Inadvertent Program Protection --Power-Up/Power-Down Protection Circuitry --Program Enable Latch --Program Protect Pin * Self-Timed Program Cycle --5ms Program Cycle Time (Typical) * High Reliability --Endurance: 100,000 Cycles/Byte --Data Retention: 100 Years --ESD: 2000V on all pins * 8-Lead SOIC Package * 8-Lead MSOP Package * 8-Lead TSSOP Package * 8-Pin Mini-DIP Package FUNCTIONAL DIAGRAM
SI SO COMMAND DECODE AND CONTROL LOGIC
The X25F047 is a CMOS 4K-bit SerialFlash, internally organized as 512 x 8. The X25F047 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. There are eight options for programmable, nonvolatile, Block Lock Protection available to the end user. These options are implemented via special instructions programmed to the part. The X25F047 also features a PP pin that can be used for hardwire protection of the part, disabling all programming attempts, as well as a Program Enable Latch that must be set before a program operation can be initiated. The X25F047 utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years.
DATA REGISTER Y DECODE LOGIC 16 8
SCK
X DECODE LOGIC
32
SERIALFLASH ARRAY (512 x 8)
CS
PP
PROGRAM CONTROL LOGIC
HIGH VOLTAGE CONTROL
7005 FRM 01.3
(c)Xicor, Inc. 1994, 1995, 1996 Patents Pending 7005-0.9 5/7/97 T4/C0/D1
1
Characteristics subject to change without notice
X25F047
PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is a serial data input pin. All opcodes, byte addresses, and data to be programmed to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25F047 is deselected and the SO output pin is at high impedance and unless a nonvolatile write cycle is underway, the X25F047 will be in the standby power mode. CS LOW enables the X25F047, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Program Protect (PP) When PP is LOW, nonvolatile writes to the X25F047 are disabled, but the part otherwise functions normally. When PP is held HIGH, all functions, including nonvolatile writes, operate normally. PP going LOW while CS is still LOW will interrupt a programming cycle to the X25F047. If the nonvolatile write cycle has already been initiated, PP going low will have no affect on this cycle. PIN NAMES Symbol CS SO SI SCK PP VSS VCC NC Description Chip Select Input Serial Output Serial Input Serial Clock Input Program Protect Input Ground Supply Voltage No Connect
7005 FRM T01
PIN CONFIGURATION
8-LEAD SOIC/DIP CS SO *0.197" PP V SS 1 2 3 4 *0.244" 8-LEAD MSOP SO 0.120" CS VSS PP 1 2 3 4 0.193" 8-LEAD TSSOP NC 0.122" VCC CS SO 1 2 3 4 0.252" *SOIC Measurement
7005 FRM 02
Not to scale V CC NC SCK SI
8 7 X25F047 6 5
8 7 X25F047 6 5
V CC NC SI SCK
8 7 X25F047 6 5
SCK SI V SS PP
PRINCIPLES OF OPERATION The X25F047 is a 512 x 8 SerialFlash designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The X25F047 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW and the PP input must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Program Enable Latch The X25F047 contains a "Program Enable" latch. This latch must be SET before a program operation is initiated. The PREN instruction will set the latch and the PRDI instruction will reset the latch (Figure 4). This latch is automatically reset upon a power-up condition and after the completion of a sector program cycle.
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X25F047
Block Lock Protection There are eight Block Lock Protection options. The predefined blocks and associated address ranges are protected by programming the appropriate two byte Program Status instruction to the device (Table 1 and Figure 6). Once a Block Lock protect instruction has been completed, that Block Lock Protection setup is held in a nonvolatile Status Register (Figure 1) until the next Program Status instruction is issued. The sections of the memory array that are Block Lock protected can be read but not programmed until Block Lock Protection is removed or changed. Figure 1. Status Register/Block Lock Protection Byte 7 0 6 0 5 0 4 0 3 0 2 BL2 1 BL1 0 BL0 clocks. CS must go LOW and remain LOW for the duration of the operation. The host must program 16 bytes in each write with the restriction that these bytes reside on one sector. If the address counter reaches the end of the sector and the clock continues, or if fewer than 16 bytes are clocked in, the contents of the sector cannot be guaranteed. For a sector program operation to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be programmed is clocked in. If it is brought HIGH at any other time, the program operation will not be completed. (Figure 5) Read Status Operation If there is not a nonvolatile write in progress, the Read Status instruction returns the Block Lock Protection byte from the Status Register which contains the Block Lock Protection bits BL2-BL0 (Figure 1). The Block Lock Protection bits define the Block Lock Protection condition (Figure 1 and Table1). The other bits are reserved and will return "0's" when read (Figure 3). If a nonvolatile write is in progress, the Read Status instruction returns the status of the internal write operation on SO. When the nonvolatile write cycle is completed, the status register data is again read out. During a nonvolatile write in progress, the SO pin will be set HIGH. At the end of the nonvolatile write cycle, SO is set to output the current bit from the status register. Clocking SCK is valid during a nonvolatile write in progress, but is not necessary. If the SCK line is clocked, the pointer to the status register is also clocked, even though the SO pin shows the status of the nonvolatile write operation (Figure 3). When the pointer reaches the end of the eight bit status register, it "rolls over" to the first bit of the register. Program Status Operation Prior to any attempt to perform a Program Status Operation, the PREN instruction must first be issued. This instruction sets the "Program Enable" latch and allows the part to respond to a Program Status sequence (Figure 6). The Program Status instruction follows and consists of one command byte followed by one Block Lock Protection byte (Figure 1). This byte contains the Block Lock Protection bits BL2-BL0. The rest of the bits [7:3] are unused and must be programmed as "0's". Bringing CS HIGH after the two byte Program Status instruction initiates a nonvolatile write to the Status Register. Programming more than one byte to the Status Register will overwrite the previously programmed Block Lock Protection byte (Table 1).
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Note: Bits [7:3] specified to be "0's"
7005 FRM T02.1
Read Sequence When reading from the SerialFlash memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25F047, followed by the 16-bit address, of which the last 9 bits are used (bits [15:9] specified to be "0's"). After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (01FFh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH (Figure 2). Sector Program Sequence Prior to any attempt to program data into the X25F047, the "Program Enable" latch must first be set by issuing the PREN instruction (Table 1 and Figure 4). CS is first taken LOW. Then the PREN instruction is clocked into the X25F047. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the program operation without taking CS HIGH after issuing the PREN instruction, the program operation will be ignored. To program data to the SerialFlash memory array, the user then issues the PROGRAM instruction, followed by the 16 bit address of the first location in the sector and then the 16 bytes of data to be programmed. Only the last 9 bits of the address are used and bits [15:9] are specified to be "0's". The entire write operation takes 152
X25F047
Data Protection The following circuitry has been included to prevent inadvertant programming of data: * The "Program Enable" latch is reset upon power-up. * A PREN instruction must be issued to set the "Program Enable" latch. * CS must come HIGH at the proper clock count in order to start a program cycle. Operational Notes The X25F047 powers up in the following state: * The device is in the low power, standby state. * A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. * SO pin is at high impedance. * The "Program Enable" latch is reset.
Table 1. Instruction Set and Block Lock Protection Byte Definition Instruction Format*
0000 0110 0000 0100 0000 0001
Instruction Name and Operation
PREN: Set the Program Enable Latch (Program Enable Operation) PRDI: Reset the Program Enable Latch (Program Disable Operation) PROGRAM STATUS Instruction - followed by: Block Lock Protection Byte: (Figure 1) 0000 0000 --->NO PROTECT: ---------------------------------->None of the Array 0000 0001 --->PROTECT Q1: --- 0000h - 007Fh ---------->Lower Quadrant (Q1) 0000 0010 --->PROTECT Q2: --- 0080h - 00FFh----------->Q2 0000 0011 --->PROTECT Q3: --- 0100h - 017Fh----------->Q3 0000 0100 --->PROTECT Q4: --- 0180h - 01FFh----------->Upper Quadrant (Q4) 0000 0101 --->PROTECT H1: --- 0000h - 00FFh----------->Lower Half of the Array (H1) 0000 0110 --->PROTECT S0: --- 0000h - 000Fh----------->Lower Sector (S0) 0000 0111 --->PROTECT Sn: --- 01F0h - 01FFh----------->Upper Sector (Sn) READ STATUS: Reads Block Lock Protection & nonvolatile write in progress status on SO Pin PROGRAM: Program operation followed by address and data READ: Read operation followed by address
7005 FRM T03.1
0000 0101 0000 0010 0000 0011
*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
Figure 2. Read Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30
READ INSTRUCTION (1 BYTE) SI
BYTE ADDRESS (2 BYTE) 15 14 3 2 1 0
DATA OUT
SO
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
7005 FRM F03.1
4
X25F047
Figure 3. Read Status Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
... ...
B L 2 SO HIGH DURING NONVOLATILE WRITE CYCLE SO = STATUS REG BIT WHEN NO NONVOLATILE WRITE CYCLE B L 1 B L 0
READ STATUS INSTRUCTION SI NONVOLATILE WRITE IN PROGRESS
SO
...
7005 FRM 04.2
Figure 4. Program Enable/Program Disable Sequence
CS
0 SCK
1
2
3
4
5
6
7
INSTRUCTION (1 BYTE) SI
SO
HIGH IMPEDANCE
7005 FRM 05.1
5
X25F047
Figure 5. Sector Program Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
PROGRAM INSTRUCTION SI
BYTE ADDRESS (2 BYTE) 15 14 13 3 2 1 0 7 6
DATA BYTE 1 5 4 3 2 1 0
CS 145 146 147 148 149 150 1 151 0
7005 FRM 07.3
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK
DATA BYTE 2 SI 7 6 5 4 3 2 1 0 7 6
DATA BYTE 3 5 4 3 2 1 0 6
DATA BYTE 16 5 4 3 2
Figure 6. Program Status Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
PROGRAM STATUS INSTRUCTION SI 0 0
BLOCK LOCK PROTECTION BYTE 0 0 0 B L 2 B L 1 B L 0
SO
HIGH IMPEDANCE
7005 ILL F08.2
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias ...................-65C to +135C Storage Temperature ........................-65C to +150C Voltage on any Pin with Respect to VSS.................................... -1V to +7V D.C. Output Current ..............................................5mA Lead Temperature (Soldering, 10 seconds) .............................. 300C
6
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
X25F047
RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Industrial
Min.
0C -40C
Max.
+70C +85C
7005 FRM T04
Supply Voltage
X25F047 X25F047-5
Limits
1.8V to 3.6V 4.5V to 5.5V
7005 FRM T05
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB ILI ILO VIL(1) VIH(1) VOL1 VOH1 VOL2 VOH2 VOL3 VOH3
Parameter
VCC Read Current (Active) VCC Write Current (Active) VCC Supply Current (Standby) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage
Min.
Max.
1 3 1 10 10
Units
mA mA A A A V V V V
Test Conditions
SCK = VCC x 0.1/VCC x 0.9 @ 1MHz, SO = Open, CS = VSS SCK = VCC x 0.1/VCC x 0.9 @ 1MHz, SO = Open, CS = VSS CS = VCC - 0.1, VIN = VSS or VCC VIN = VSS to VCC VOUT = VSS to VCC
-0.5 VCC x 0.7
VCC x 0.3 VCC + 0.5 0.4
VCC = 5.5V, IOL = 2.1mA VCC = 5.5V, IOH = -1.0mA VCC = 3.6V, IOL = 1.0mA VCC = 3.6V, IOH = -0.4mA VCC = 1.8V, IOL = 0.5mA VCC = 1.8V, IOH = -0.25mA
7005 FRM T06
VCC - 0.8 0.4 VCC - 0.4 0.4 VCC - 0.2
V V V V
POWER-UP TIMING Symbol
tPUR(3) tPUW(3)
Parameter
Power-up to Read Operation Power-up to Write Operation
Min.
Max.
1 5
Units
ms ms
7005 FRM T07.1
CAPACITANCE TA = +25C, f = 1MHz, VCC =5V. Symbol
COUT
(2)
Parameter
Output Capacitance (SO) Input Capacitance (SCK, SI, CS, PP)
Max.
8 6
Units
pF pF
Conditions
VOUT = 0V VIN = 0V
7005 FRM T08
CIN(2)
Notes: (1) VIL Min. and VIH Max. are for reference only and are not 100% tested. (2) This parameter is periodically sampled and not 100% tested. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
7
X25F047
EQUIVALENT A.C. LOAD CIRCUIT
5V 2061 OUTPUT 3025 2696 OUTPUT 5288 3.3V
A.C. TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Level
30pF
VCC x 0.1 to VCC x 0.9 10ns VCC X 0.5
7005 FRM T09
30pF
7005 FRM 09.1
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Data Input Timing Symbol
fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(4) tFI(4) tCS tWC(5)
Parameter
Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Data In Rise Time Data In Fall Time CS Deselect Time Write Cycle Time
Min.
0 1000 500 500 400 400 100 100
Max.
1
Units
MHz ns ns ns ns ns ns ns s s s
2 2 2.0 10
ms
7005 FRM T10
Data Output Timing Symbol
fSCK tDIS tV tHO tRO(4) tFO(4)
Parameter
Clock Frequency Output Disable Time Output Valid from Clock LOW Output Hold Time Output Rise Time Output Fall Time
Min.
0
Max.
1 500 400
Units
MHz ns ns ns
0 300 300
ns ns
7005 FRM T11
Notes: (4) This parameter is periodically sampled and not 100% tested. (5) tWC is the time from the rising edge of CS after a valid program sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
8
X25F047
Figure 7. Serial Output Timing
CS t CYC SCK tV SO MSB OUT MSB-1 OUT t HO t WL LSB OUT t DIS t WH t LAG
SI
ADDR LSB IN 7005 FRM 10
Figure 8. Serial Input Timing
tCS CS t LEAD SCK tSU SI MSB IN tH tRI t FI t LAG
LSB IN
HIGH IMPEDANCE SO
7005 FRM 11
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
9
X25F047
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49)
0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) 0.020 (0.50) X 45
0.050" TYPICAL
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL 8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
10
X25F047
PACKAGING INFORMATION 8-LEAD MINIATURE SMALL OUTLINE GULLWING PACKAGE TYPE M
0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) TYP
R 0.014 (0.36)
0.118 0.002 (3.00 0.05)
0.030 (0.76) 0.0216 (0.55)
0.036 (0.91) 0.032 (0.81)
7 TYP
0.040 0.002 (1.02 0.05)
0.008 (0.20) 0.004 (0.10)
0.007 (0.18) 0.005 (0.13)
0.150 (3.81) REF. 0.193 (4.90) REF.
NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
3003 FRM 01
11
X25F047
PACKAGING INFORMATION 8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.114 (2.9) .122 (3.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
12
X25F047
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25)
0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
0.015 (0.38) MAX.
0.325 (8.25) 0.300 (7.62)
TYP. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
13
X25F047
ORDERING INFORMATION X25F047 Device P T -X VCC Range Blank = 1.8V to 3.6V 5 = 4.5V to 5.5V Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C Package S = 8-Lead SOIC M = 8-Lead MSOP V = 8-Lead TSSOP P = 8-Lead Plastic DIP 8-Lead TSSOP EYWW 5F47XX Blank = 1.8 to 3.6V, 0C to +70C I = 1.8 to 3.6V, -40C to +85C AE = 2.5 to 5.5V, 0C to +70C AF = 2.5 to 5.5V, -40C to +85C 5 = 4.5 to 5.5V, 0C to +70C I5 = 4.5 to 5.5V, -40C to +85C 8-Lead SOIC/PDIP X25F047 X XX Blank = 8-Lead SOIC P = 8-Lead Plastic DIP
Part Mark Convention 8-Lead MSOP EYWW XXX AAH = 1.8 to 3.6V, 0C to +70C AAI = 1.8 to 3.6V, -20C to +85C AAJ = 1.8 to 3.6V, -40C to +85C AAK = 2.5 to 5.5V, 0C to +70C AAL = 2.5 to 5.5V, -40C to +85C AAM = 4.5 to 5.5V, 0C to +70C AAN = 4.5 to 5.5V, -40C to +85C
LIMITED WARRANTY
Blank = 1.8 to 3.6V, 0C to +70C I = 1.8 to 3.6V, -40C to +85C AE = 2.5 to 5.5V, 0C to +70C AF = 2.5 to 5.5V, -40C to +85C 5 = 4.5 to 5.5V, 0C to +70C I5 = 4.5 to 5.5V, -40C to +85C
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 14

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